In the computer industry, on-board memory is conventionally coupled to a processor through a memory channel. Along those lines, a motherboard may have multiple memory slots for multiple memory modules, such as SIMMs or DIMMs, for a channel. More recently, processors are capable of handling more than one memory channel. Some processors are capable of being coupled to two or four memory channels.
One reason for going to multiple channels is to effectively reduce loading effects for operation at higher memory interface speeds. For example, if one DIMM is coupled via one channel, the loading effects may not be appreciably large to prevent higher-stock or over-clocking speeds for operation. However, if a second DIMM is added to that same memory channel in this example, then loading effects caused by addition of such second DIMM can substantially reduce operational speed for communication with such DIMMs. This problem may become worse with each additional memory module added onto a channel. Hence, some processors support multiple channels to reduce the number of DIMMs per channel while allowing for a significant number of DIMMs to increase on-board memory, such as system memory for example. However, adding support for additional channels complicates both processor design and motherboard design.
Others have suggested buffering addresses and data on a memory module to reduce loading effects to provide a load reduced memory module, such as for example LRDMMs. Effectively, buffering transfers loading effects from a channel having multiple memory slots onto each memory module. Some of these buffered memory modules have centrally located buffers similar to registered memory modules, such as for example RDIMMs. In addition to buffering I/O data, these central memory buffers may buffer and retransmit command, address, and clock signals to memory dies of such memory module. Other configurations may have a centrally located registered clock driver (“RCD”) with distributed data buffers to provide such data I/O loads more locally to edge connector pads and associated memory dies. These shorter trace lengths may increase data path speed and signal integrity while reducing latency on a memory channel bus. However, buffering not only adds additional circuitry, which may be in the form of additional chips, to a memory module, such buffering may also increase operational latency of a memory module in comparison to an unbuffered memory module, such as a UDIMM for example. Thus, if only one memory module is located on a channel, a load reduced memory module may be slower than a more conventional unbuffered memory module.
Accordingly, it would be desirable and useful to provide a memory module which may be added to a channel that has less impact on performance without substantially increasing cost and/or increasing latency.